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 Aldec Design and Verification
Henry Chan
Henry Chan
Henry provides support and guidance to Aldec customers as an Applications Engineer. Specializing in Active-HDL™ and Riviera-PRO™, he is well versed in Aldec’s industry leading FPGA design and simulation tools. His diverse knowledge from hardware description languages to functional … More »

U.V.M. Spells Relief

 
December 4th, 2015 by Henry Chan

blog_120215Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly.

So what is UVM?

UVM stands for universal verification methodology and is based on an earlier verification methodology (OVM 2.1.1 developed by Cadence and Mentor Graphics). Accellera used this OVM base, continued development, and now maintains it as a more modern and updated version in UVM. Tangibly, UVM is a library of SystemVerilog code that is intended to help engineers write effective test and verification environments. You can download the UVM class library code, user guide, and reference documents from Accellera’s website.

Key Benefits of UVM:

  1. Constrained Random Stimulus

The problem is: testing all possible combinations of a design’s signals will take too long to simulate. UVM addresses this by constraining the stimulus to certain values and randomizing specific cases for maximum coverage. The control you have over your test pattern generation is unprecedented. Generating customized sequences of signals that will push your design into desired corner cases is easy with UVM.

  1. Code Reuse

UVM was designed to provide a ton of ‘boilerplate’ code that can be reused. There is no longer a need to start from scratch for each different design. Make efficient use of your time by copying and pasting a verification environment from a previous project and simply make small adjustments.

  1. Standard Verification Methods

As UVM adoption proliferates, verifying your designs using a standard methodology provides consistency among the engineering community. Your verification environment will be understood by other engineers, including team members. Send your files to others without having to explain your verification methods. You will even be able to troubleshoot your verification environment by visiting forums dedicated to UVM for information.

For the rest of this article, visit the Aldec Design and Verification Blog.

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Category: Functional Verification

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