Aldec Design and Verification
Krzysztof Szczur is a Hardware Technical Support Manager. He joined Aldec in 2001 and was a key member of the team that developed HES™, Aldec's FPGA-based co-simulation and emulation technology. He has worked in the fields of HDL IP-cores verification, testbench automation and design verification … More »
Emulation: Thinking outside of the Big Box
September 22nd, 2015 by Krzysztof Szczur
Independent FPGA Consultant, Doug Amos, has been working in programmable logic and FPGA for over 30 years. He did his first programmable logic design in the mid-80’s (around the time Aldec was born), and since then has designed or supported countless FPGA and ASIC designs.
We’ve been pleased to work with Doug over the past several months, to help tell the story of Aldec’s advanced hardware emulation and SoC and ASIC prototyping solutions. Here is a excerpt from Doug’s recent guest blog:
There’s no question; verification is a massive time drain in SoC and other chip design projects. For many years, those with deep enough pockets have turned to so-called “Big Box” emulators in order to recover some of the time lost on RTL simulation, but what about the rest of us? Is there another way to accelerate verification and reduce our overall project schedule? Yes there is; and at Aldec they call it FPGA-based Emulation.
“FPGAs; aren’t they just for prototyping?”
Sure, FPGAs are the fastest platform for prototyping, but we can also harness that speed into our verification environment, then we can achieve runtime performance 2x to 5x faster than traditional “big box” emulation systems, and all at a fraction of the cost per gate per MHz. The most significant differences between FPGA usage in prototypes and in emulation is shown in table 1.
Table 1: Typical differences between FPGA usage in prototyping and emulation
“FPGAs are way too small for our SoC design, aren’t they?”
For the rest of this article, please visit the Aldec Design and Verification Blog.