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 Aldec Design and Verification
Satyam Jani
Satyam Jani
Satyam manages Aldec’s leading FPGA design entry and simulation tool – Active-HDL. He received his B.S. in Electronics Engineering from Sardar Patel University, India in 2003 and M.S in Electrical Engineering from NJIT, New Jersey in 2005. His practical engineering experience includes areas in … More »

The Pythonic Tonic: Miracle cure or Snake-oil?

 
May 20th, 2015 by Satyam Jani

python-logoPython is making inroads in the EDA landscape, but is all the hype justified? Do the productivity benefits of a dynamic language translate to gains for real-world development for ASIC and FPGA designs? Chris Higgs of Potential Ventures will be onsite at DAC to share his experiences using Python and Aldec Riviera-PRO to take products from idea to production quickly.

Chris recently wrote a Guest Blog on the topic, visit the Aldec Design Verification Blog to learn more.

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Category: Functional Verification

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