Aldec Design and Verification
Kamil Rymarz, Hardware Design Engineer. Kamil joined Aldec in 2011 and, has specialized in creating reliable verification IPs. He has practical experience in SCE-MI co-emulation and in-circuit emulation. Kamil received his Masters of Engineering at AGH University of Science and Technology in … More »
How Can Verification IPs Help the SoC Testing Process?
April 20th, 2015 by Kamil Rymarz
How to use VIPs In Practice
Allow me to describe a typical verification process, and explain why I recommend the use of Verification IPs within the testing process.
Unfortunately, due to limited computing power and the growing complexity of modern designs, simulation is not fast enough for long and complex tests. It is mainly used to verify each component separately with a limited scope of tests. Simulation of the whole design would require a lot of time, even for simple test scenarios. However, design schedules can rarely be extended or prolonged, so engineers need to find a faster way to check the whole system on chip.
works. Simulating it would take too much time, so we are going to use hardware emulation instead. Fortunately, we don’t have to avoid using UVM in emulation, because well-designed transactors can be used in the same way as in simulation.
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