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 Aldec Design and Verification

Archive for April 20th, 2015

How Can Verification IPs Help the SoC Testing Process?

Monday, April 20th, 2015

 

How to use VIPs In Practice

figure 0
Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers.

Allow me to describe a typical verification process, and explain why I recommend the use of Verification IPs within the testing process.

Figure1 typical verification process
Figure 1. Typical verification process

(more…)

DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
DownStream: Solutions for Post Processing PCB Designs



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