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Krzysztof Szczur
Krzysztof Szczur
Krzysztof Szczur is a Hardware Technical Support Manager. He joined Aldec in 2001 and was a key member of the team that developed HES™, Aldec's FPGA-based co-simulation and emulation technology. He has worked in the fields of HDL IP-cores verification, testbench automation and design verification … More »

How HES™ Technology Solved Problems for These Users

October 20th, 2014 by Krzysztof Szczur

HES_USE_CASESRecognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003, integrating RTL simulation with hardware emulation, and offering hardware and software design teams the ability to work concurrently. Today HES™ is a fully automated and scriptable HybridVerification and Validation environment for SoC and ASIC designs capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling.

Aldec_Use_Case_Fabless_SemiconductorUse Case #1 – A Fabless Semiconductor Company

In this case, the user had many requirements including the verification of a 20 million gate design in bit level acceleration and SCE-MI transaction level emulation, and also required extensive debugging functions. The verification process was performed using HES technology (DVM, transactors and HES boards) in acceleration and SCE-MI emulation with all required debugging features, memory support and Virtual Platform integration. [More Use Case Details]

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Categories: SoC and ASIC Prototyping, SoC Design and Validation

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