Aldec Design and Verification
Ajay is a Product Manager at Aldec for DRC and CDC solutions. He received his BS in Electrical Engineering from the National Institute of Technology, Jaipur, India and has 18 years of experience in the ASIC/FPGA and EDA industry. Ajay has worked for various companies in San Jose such as Xilinx, Mentor Graphics, Actel, Microsemi and Real Intent, and is experienced in roles such as as Design Engineer, Senior VLSI Engineer, Field and Corporate Application Engineering, Design Solutions, as well as building a Corporate Application Engineering Team from the bottom up as Manager of CAE at MicroSemi. « Less
Ajay is a Product Manager at Aldec for DRC and CDC solutions. He received his BS in Electrical Engineering from the National Institute of Technology, Jaipur, India and has 18 years of experience in the ASIC/FPGA and EDA industry. Ajay has worked for various companies in San Jose such as Xilinx, … More »
Averting CDC Roadblocks in FPGA Design
September 19th, 2014 by Ajay Pradhan
This being my first summer in Las Vegas, it is the first time I’ve experienced the rainy, desert monsoon season and the powerful flash floods it can bring. Last week one of those monsoons, powered by the remnants of Hurricane Norbert, produced floodwaters so strong they completely washed out a section of the I-15 Interstate north of town. With no road for several days, those traveling to and from Utah were forced to take a long detour, winding through nearby towns and wasting precious travel time.
An effective CDC solution for design rule checking can work much the same way, like a straight, clearly marked highway that quickly delivers you directly to your destination. Without such a solution, detouring past the many CDC issues that are becoming more pervasive in FPGA design can quickly become a long, winding road – and an inefficient use of time and resources. I covered some of these CDC nightmares in a previous article, and in this post I’ll share some best practices to help avoid these roadblocks. I’ll also demonstrate how new CDC rule plugins (to be added later this year to ALINT™) can help in the mitigation of such issues.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, alint, cdc design rule checks, cdc related failure, clock domain crossing issue, do-254, fpga device, fpga-based soc design complexity, linting, metastability issues, multiple clock domains, rmm, simulation, starc
Category: Functional Verification