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 Aldec Design and Verification
Sunil Sahoo
Sunil Sahoo
Sunil is Corporate Applications Engineer at Aldec. Sunil provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide … More »

Simulate UVM & SystemVerilog online for free

August 19th, 2014 by Sunil Sahoo

Aldec-on-EDA-Playground-200-170During a recent trip to Austin, Texas, I spent some time with Aldec Partner, Victor Lyuboslavsky of Victor EDA and creator of the EDA Playground. Victor EDA is one of those organizations that Aldec aligns easily with because we share a strong commitment to accelerate learning within the engineering community by providing the right tools, training and resources.

As a result of this partnership, we are pleased to announce that Aldec Riviera-PRO EDU™ Advanced Verification Platform is now available on EDA Playground.

Here’s an excerpt from Victor’s recent guest blog post on the Aldec Design and Verification Blog, that illustrates how engineers can benefit from leveraging this tool to practice UVM & SystemVerilog simulation:

You may have found yourself among those eyeing the job market and wondering, “How hard is it to switch fields and become a verification engineer?”

It can be difficult, as it turns out.

But it can be done if you are committed to following the steps:

  1. Learn the basics of HDL design and verification. This part is fairly straightforward and can be picked up from books and web resources.
  2. Practice. It’s vital to actually “do the work” so that you are able to answer hands-on interview questions. Unfortunately, it is surprisingly difficult to practice simulating UVM and SystemVerilog unless you have access to university licenses, are already working for a semiconductor company, or are fortunate enough to have a high-level friend at one of the simulator vendors.
  3. Join a community. To give you a competitive edge it is important to become part of a community of like-minded engineers, who are willing to help each other out without a corporate agenda.

Not long ago, I myself was preparing for job interviews and working to ramp up on SystemVerilog and UVM. I used the web to find code examples and tutorials. However, the examples were often incomplete. Occasionally they were missing the necessary code to hook the example into a real design. Other times, the code examples had syntax errors – I might be presented with a supposedly working design, with lines stripped out, but with undefined variables and dangling commas left in. Other times the code examples simply did not work on my simulator. The result was endless frustration for the student in me.

I knew there had to be a better way…

For the rest of this post, we invite you to visit the Aldec Design and Verification Blog.

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