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Krzysztof Szczur
Krzysztof Szczur
Krzysztof Szczur is a Hardware Technical Support Manager. He joined Aldec in 2001 and was a key member of the team that developed HES™, Aldec's FPGA-based co-simulation and emulation technology. He has worked in the fields of HDL IP-cores verification, testbench automation and design verification … More »

FPGA-Based Prototyping Q&A: 100 Million Gates and Beyond

July 30th, 2014 by Krzysztof Szczur


I am a Hardware Technical Support Manager. Ask Me Anything!

Earlier this summer, I joined a team traveling from Aldec’s R&D offices in Kraków, Poland to attend the annual Design Automation Conference (DAC) in San Francisco. As Technical Support Manager for Aldec’s Hardware Products Division, my goals for this event were two-fold. First, as we’ve made huge enhancements to our HES-7™ FPGA prototyping solution in the past year, I wanted to be there in person to share more about them in demos and presentations at the Aldec booth.

Secondly, and really my favorite part of DAC, I wanted to hear from engineers in the field looking for solutions to their real-world problems. Sometimes I have immediate answers for their questions, like the engineer who was not happy with their current solution’s implementation time or the fellow that needed support for in-house development boards. Occasionally though, I don’t have an immediate answer and instead they’ve given me valuable ideas that I get to take back home to my team so we can set to work developing solutions.

To say I was busy at DAC was an understatement, as we had three non-stop days of meetings. Still, there were so many people that I didn’t get to meet, not to mention those who did not attend DAC at all. Which brings me to my proposal – if you have FPGA-Based Prototyping questions that you would like to have answered, I’d like to invite you to send me your questions and register for Aldec’s upcoming live webinar event:

Live Webinar:

FPGA-Based Prototyping Q&A: 100 Million Gates and Beyond

Date: Thursday, August 7, 2014

Register for EU 3:00 PM – 4:00 PM CEST

Register for US 11:00 AM – 12:00 PM PDT

Visit this survey link to send me your burning FPGA-Based Prototyping questions, and I will do my best to answer them at this live event.

If you are interested, I’ll be doing the same thing on the topic of SoC Emulation on September 11, 2014. Visit the Aldec Webinar Calendar for more.

For the rest of this article, visit the Aldec Design and Verification Blog.

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Category: SoC and ASIC Prototyping

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