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Bill Jason
Bill Jason
Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for … More »

Integrating SystemVerilog and SCE-MI for Faster Emulation Speed

October 9th, 2013 by Bill Jason

In the last SCE-MI article, we discussed how SCE-MI macro-based infrastructures can speedup SoC design verification time. In SCE-MI 2.1, Accelera introduced a ‘function-based’ infrastructure which is based on SystemVerilog DPI functionality. The SystemVerilog DPI is an interface which can be used to connect SystemVerilog files with foreign languages (C, C++, SystemC, etc).

This new interface provides users with multiple benefits when dealing with an emulation environment including:

  • No Pre-defined Emulation API

In macro-based SCE-MI, the user is held to a pre-defined C/C++ API which can be used to interface with synthesizable macros implemented in the hardware emulator.  Such components included SceMi initialization and shutdown, messing input/output port proxy binding, error handling, etc.  SystemVerilog DPI uses simple function calls as a mechanism for inter-language communication. This enables the user more flexibility to create their own API, defining the functions in one language and calling them in another.

  • The Function Call is the Transaction

During communication between high-level testbench and signal-level DUT, the functional call itself is the transaction, along with the function call arguments (inputs and outputs) being the transactions data members. This avoids having to use slices and bit fields of a single large vector which is used in macro-based SCE-MI.  Although the SystemVerilog LRM allows for a multiple range of data types to be passed for function arguments, SCE-MI restricts to a subset containing bit vectors and integers.

For the rest of this article, visit the Aldec Design and Verification Blog.

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Categories: Emulation/Acceleration, SoC Design and Validation

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