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 Aldec Design and Verification
Jerry Kaczynski
Jerry Kaczynski
Jerry serves as Aldec’s Research Engineers and possesses over 20 years of experience in HDL language & tool training, technical writing, application and research engineering. He is an IEEE and Accellera committee member, involved in the development of industry standards for VHDL, Verilog, … More »

HW Designers: Brush up on your SV with Online Training

August 12th, 2013 by Jerry Kaczynski

Fast Track to SystemVerilog for Verilog Users

The ability to adopt methodologies and get up to speed quickly is critical in today’s fast moving environment. Aldec offers Fast Track™ ONLINE trainings designed for busy engineers to increase their productivity and enhance their skill level from the comfort of their own browser.

Got SystemVerilog? While it may be a fashionable topic among verification engineers, it’s generally a shunned subject among hardware designers. While there are many good reasons for this (overgrown size of the SystemVerilog standard, expensive options required to use many language features in simulation, poor support in low-end tools, etc.), designers familiar with classical Verilog can benefit greatly from the features available in the Design Subset of SystemVerilog. Designing state machines is one excellent example. It is as easy and elegant in SystemVerilog as it is in VHDL – and those machines even synthesize in better tools!

Aldec’s most recent Fast Track online training, Fast Track to SystemVerilog for Verilog Users, is available at no cost for all registered users. It assumes good knowledge of classic Verilog and shows all SystemVerilog enhancements that can be used in everyday coding.

It’s easy to get started. Here’s a sneak peek at the Fast Track Online Training interface:

Clicking a highlighted entry on the side bar or Read more link in the brief training description jumps to the selected training page.

Clicking the Get started link opens a list of available modules.

In this example, Module 1: General has been completed. This means the student has viewed the entire module presentation and successfully completed the test at the end. The module can be reviewed at any time, but test at the end will not show up again.

The Module 2: Arrays is not yet marked completed, so the student did not yet pass the test. Each module access requires completion of previous modules, so the remaining two modules are not accessible at this time.

Note the Feedback link at the bottom right-hand corner on each page. Feedback is appreciated, please use this link if you notice any issues or have suggestions for improvement.

Once you click on the next module, you are transferred to the presentation slides.

Presentations are not only text-based but enhanced with diagrams and examples.

Clicking anywhere on a presentation slide advances to the next page.  You can also use Previous Page / Next Page buttons or the left sidebar to navigate.

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Categories: FPGA Design, Functional Verification

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