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 Aldec Design and Verification

Archive for August 12th, 2013

HW Designers: Brush up on your SV with Online Training

Monday, August 12th, 2013

 

Fast Track to SystemVerilog for Verilog Users

The ability to adopt methodologies and get up to speed quickly is critical in today’s fast moving environment. Aldec offers Fast Track™ ONLINE trainings designed for busy engineers to increase their productivity and enhance their skill level from the comfort of their own browser.

Got SystemVerilog? While it may be a fashionable topic among verification engineers, it’s generally a shunned subject among hardware designers. While there are many good reasons for this (overgrown size of the SystemVerilog standard, expensive options required to use many language features in simulation, poor support in low-end tools, etc.), designers familiar with classical Verilog can benefit greatly from the features available in the Design Subset of SystemVerilog. Designing state machines is one excellent example. It is as easy and elegant in SystemVerilog as it is in VHDL – and those machines even synthesize in better tools!

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