Aldec Design and Verification
Dmitry is a product manager at Aldec responsible for ALINT™ and Riviera-PRO™ product lines. He has over 8 years of digital design and verification experience, including previous roles in corporate and field applications, technical marketing, and software development with R&D divisions of … More »
‘Wireless Algorithm Validation’ with Aldec and Agilent
May 30th, 2013 by Dmitry Melnik
Free DAC INSIGHT Presentation
At the fast-approaching Design Automation Conference (DAC) 2013 in Austin, TX, Aldec will co-host an INSIGHT Session with Agilent Technologies on how to validate a digital signal processing algorithm for both floating and fixed point levels. As Riviera-PRO Product Manager, I will join Agilent Senior Product Marketing Engineer FAE, Sangkyo Shin, on Wednesday, June 5th at 2pm in presenting a combined Agilent/Aldec FPGA flow that can be used to quickly validate communications digital signal processing (DSP) algorithms and accelerate physical layer (PHY) performance measurements.
Mr. Shin will review the system-level design challenges and how to solve them using the SystemVue™ software, which provides the capabilities needed to evaluate and design modern communication systems and related products. I will then take the auto-generated HDL code from a system-level concept down to HDL simulation in Aldec Riviera-PRO™ and FPGA implementation on Aldec HES-5™ hardware prototyping board. Attendees will gain valuable insight on the cross-domain approach to traditional FPGA design flow and learn how to validate FPGA design for leading edge wireless and radar system with a system-level simulation tool integrated into the traditional hardware design flow.
Here are some of the highlights we will review on the HDL/HW side:
We will also benchmark HDL vs. HIL simulation and explain how to optimize your HDL design for efficient HIL simulation.
If you will be in attendance in Austin this year, join us for this complimentary session. INSIGHT Session are available at no extra cost to all attendees, guests, and staff members, simply select the appropriate session when registering for DAC.
You may also register for Technical Sessions and Demonstrations at Aldec’s Booth #2225. Learn more at www.aldec.com/dac2013.
Tags: accelerate physical layer phy performance measurements, agilent, Aldec, aldec hes 5 hardware prototyping board, dac, debugging, dsp algorithms, FPGA, fpga design flow, hardware design flow, hdl debugging tools, hdl simulation, Riviera-PRO, riviera-pro product manager, systemvu software, validate communications digital signal processing, validate design, wireless algorithm validation