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 Custom Layout Insights  by Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells, Director of Product Marketing at Synopsys
Reducing Analog Cell Layout Time with the Symbolic Editor
Hello again! In the last blog post I profiled the use of Custom Compiler's Symbolic Editor for rapid digital cell layout. In this post, we will tackle analog cell layout and show some more of the Symbolic Editor features that enable analog …

 Hardware Emulation Journal  by Lauro Rizzatti
Lauro Rizzatti
European User Group Offers Memorable Keynotes, Practical Technical Sessions
Continuing a tradition started in the early days of the company, the European edition of the Mentor Graphics’ User Group meeting, now renamed User2User or U2U, was held Tuesday, October 11, in Munich, Germany. In the opening remarks Matthias …

 IP Showcase  by Peggy Aycinena
Peggy Aycinena
REUSE 2016: Addressing the Four Freedoms
  On Thursday next week, December 1st, the IP community is going to launch its own IP-centric conference, REUSE 2016. It's an important moment: Can the conference live up to its potential, provide a unique venue for discussions of this …

 Bridging the Frontier  by Bob Smith, Executive Director
Bob Smith, Executive Director
A Busy December with REUSE 2016, Updates to Multi-Die IC Design Guide, New Member Outreach
While 2016’s coming to an end, it’s not quite over yet and the month of December will be busy for the ESD Alliance. Our industry has one brand new event called REUSE 2016 that will take place Thursday, December 1. The ESD Alliance will be …

 What Would Joe Do?  by Peggy Aycinena
Peggy Aycinena
Retail Therapy: Jump starting Black Friday
  It's no secret that my 5-year old laptop died recently; the cries of anguish could be heard a mile away. What to do? Step 1: Boot the system off Fedora on a data-stick, recover the lost files, and move on. To do that required the …

 Embedded Software  by Colin Walls
Colin Walls
Choosing an embedded operating system
I was recently approached for help by a Mentor Graphics customer, who was planning a new project and needed to select an operating system. They wanted guidance with that choice. Of course, one is tempted to say that it does not matter which of our …

 Aldec Design and Verification  by Zibi Zalewski, General Manager, Hardware Division
Zibi Zalewski, General Manager, Hardware Division
An Easier Path to Faster C with FPGAs
For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. What happens when a subject matter expert creates a powerful model …

 Guest Blogger  by Michael (Mac) McNamara, Gen Chair 54th DAC; Pres & CEO Adapt-IP
Michael (Mac) McNamara, Gen Chair 54th DAC; Pres & CEO Adapt-IP
#54 DAC, 2: Executive committee members you need to know (and your first slate of deadlines)
Time is the only critic without ambition. – John Steinbeck Like many things, DAC looks decidedly different depending on where you sit, and how you experience it.  As an attendee, it’s mostly a few days at the start of every summer where you …

 The Breker Trekker  by Adnan Hamid, CEO of Breker
Adnan Hamid, CEO of Breker
EDA Hates C++. Wait, What – Back Up!
Why is Accellera supporting the use of an industry standard language in the development of the Portable Stimulus Standard? Read the rest of this entry »

 EDA Careers Corner and News  by Mark Gilbert
Mark Gilbert
Hiring Process in EDA has changed…The Right Recruiter DOES Make a REAL Difference…
Making a job change is rarely an easy decision, admittedly though, so wonderful when it is. For the majority of you that have to work at it to land that next opportunity, much of your success lies in your ability to properly present yourself.  …

 Real Talk  by Lisa Piper, Senior Technical Marketing Manager at Real Intent
Lisa Piper, Senior Technical Marketing Manager at Real Intent
Fix X-pessimism in Netlists with Practical Techniques
Most functional verification is done before the RTL is handed off for digital synthesis. Gate-level simulations take longer and are hard to debug, but still needed to verify some circuit behavior. Ideally, the output of the RTL simulation will match …

 Decoding Formal  by Pippa Slayton
Pippa Slayton
Another Reason to Stay an Extra Day in Austin
If you are attending the Design Automation Conference (DAC) in Austin, Texas, June 5-9, and need a good reason to stay an extra day, look no further. Oski Technology is offering a one-day primer on advanced formal verification techniques at the …

 What's PR got to do with it?  by Ed Lee
Ed Lee
What is in-situ de-embedding?
As a follow up to Chris Scholz’s predictions on 2016 signal integrity trends, we checked in with in-situ de-embedding inventor Dr. Ching-Chao Huang, who gives us a more detailed look at how engineers will need to handle signal integrity …

 Analog Insights  by Hélène Thibiéroz
Hélène Thibiéroz
Q&A with Altera: How to improve your advanced-node design productivity using Synopsys SPICE Simulation and Analysis environment
Greetings, You may have noticed from my previous post that we had a very successful event in Austin. I therefore wanted to share with you some of the technical content.  One of the aspects we cover is the increasing amount of analysis and …

 The Dominion of Design  by Sanjay Gangal
Sanjay Gangal
Median Income of Electrotechnology, IT Professionals Rises to $130,000 for Largest Gain in Past Five Years
Article source: IEEE Median income for electrotechnology and information technology professionals jumped by more than 4 percent in 2014, the largest increase in the past five years, according to the 2015 IEEE-USASalary & Benefits …

 Video Roundup  by Susan Smith
Susan Smith
HP Announces HP Z240 Tower and Z240 SFF Workstations
Jeff Wood - vice president, WW Product Management,  Workstation and Thin Client Business HP and Josh Peterson- director, WW Product Management,  Workstation and Thin Client Business , HP met with the press in a virtual press briefing prior to the …

 Verification Futures  by Mike Bartley
Mike Bartley
DVCon India expected to welcome over 600 delegates
The second DVCon India Conference is expecting to welcome over 600 delegates , up from 450 last year for the first conference. It is running in Bangalore on September 10th and 11th. But why should you be there too? 39 technical papers and 15 …

 Core Values  by Neil Parris
Neil Parris
7 things I learned at 52DAC
Last week I attended the Design Automation Conference as an intrepid reporter to put my ear to the ground and take note of what is happening in the industry. I wrote some daily review blogs of my time on the show floor (which can be seen here, Day …

 Disrupted Hard  by Matthieu Wipliez
Matthieu Wipliez
Numbers don’t lie: there is virtually no interest in high level synthesis
I finally read enough articles about high level synthesis (HLS) that give a sense of hype that just didn't seem to be matched by what I've heard. Now hype is pretty subjective, but numbers are not. For example, the High Level Synthesis group on …

 ExcelliBlog  by Rick Eram, Sales & Marketing VP
Rick Eram, Sales & Marketing VP
Value of timing constraints files beyond STA
Timing Constraint files are one of the best timing and clock data containers available to the designers, yet they are under utilized today and their value is not fully exploited in the design flow. The timing information captured in timing …

 The Instigater: Services with a Smile  by Arman Poghosyan
Arman Poghosyan
EDA Application Porting Guide: Part 1
Introduction With this article we would like to start a series of tutorials covering the migration of EDA applications from Windows to Mac OS X and GNU/Linux. For that purpose we will review the technologies for building user-interface, data layer …

 ASIC with Ankit  by Ankit Gopani
Ankit Gopani
Class – The Classic Feature – Part II
Dear AWA Readers Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test …

 NOT EDA  by Sanjay Gangal
Sanjay Gangal
Satya Nadella Named Microsoft CEO
Article source: Microsoft Corp. & Wikipedia Microsoft Corp. today announced that its Board of Directors has appointed Satya Nadella as Chief Executive Officer and member of the Board of Directors effective immediately. Nadella previously …

 It's Verific !  by Michiel Ligthart
Michiel Ligthart
The demise of VHDL has been greatly exaggerated
I don’t recall when it was the first time that I heard VHDL was a dying language, but for sure it was many years ago, maybe as far back as the late 1990s. Obviously the EDA futurists of then got it very wrong, and I was recently wondering if I …

 AWR Insights  by Sherry Hess
Sherry Hess
AWR: Redefining Design
When I first learned of NI’s Redefining campaign, I thought… yes, makes perfect sense and fits AWR extremely well. Our company was founded almost 20 years ago on the very idea of redefining design for microwave/RF engineers. We began this …

 Dispatches from Boston  by Nanette Collins
Nanette Collins
OneSpin Reaches for the Cloud
As the 50th Design Automation Conference opens, attendees rushing through the doors early Monday may have their heads in a Cloud. Cloud computing that is, and heading straight toward Booth #846. That’s because OneSpin Solutions in Booth #846 …

 Verification is No Simulation  by Dave Rich
Dave Rich
Get your IEEE 1800-2012 SystemVerilog LRM at no charge
At this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge …

 Industry Commentary  by Dr. Russ Henke
Dr. Russ Henke
The EDA and MCAD/MCAE Almanac – Nominal Q3 2012 Part B: MCAD/MCAE Industry
Dear faithful blog reader: Please take a few minutes of your valuable time to read the January 31, 2013 article, “The EDA and MCAD/MCAE Almanac - Nominal Q3 2012 Part B: MCAD/MCAE Industry” You may reach the new January 31 Commentary by …

 IEEE CEDA Corner  by Joel Phillips
Joel Phillips
Alberto Sangiovanni-Vincentelli Celebrates ICCAD’s 30th Anniversary with Look Back at EDA
CEDA turned to Alberto Sangiovanni-Vincentelli of the University of California, Berkeley, to help us celebrate the 30 anniversary of the International Conference in Computer-Aided Design (ICCAD). And, he didn’t disappoint. In a rousing talk …

 EDA Thoughts  by Daniel Payne
Daniel Payne
DAC 2011 Trip Reports – Mostly Transistor Level Tools
2011 was the year of the foundry (TSMC, Globalfoundries, Samsung) at DAC in San Diego. The foundries had bigger booths, bigger events, were on more panel sessions, and had more marketing influence than any other year that I can remember. The …

 Global Business in EDA  by Mo Casas
Mo Casas
Are you missing the opportunity to go global? These tips will signal if you are ready
Expanding business overseas is important. If you are a small EDA vendor, going global before you are ready can be suicidal. Here are some signals that can help you decide you if you are ready to go global. Have you been successful at …

 Become Your Customers  by Saranyan Vigraham

 Open Electrons  by Chitlesh Goorah (Free Electronic Lab)
Chitlesh Goorah (Free Electronic Lab)
Milkymist: pushing further the limits of electronics openness
Everyone has heard of open source software, but can the same principles be applied to hardware? Some people argue that hardware is so expensive to manufacture and modify that it prevents hobbyists from contributing, and thus stifles …

 Stan on Standards  by Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski, Group Director of Standards, Cadence
Japan & SystemC
With all of the excitement in the “front end” of the SOC design/verification/modeling community about Accellera’s UVM, it is easy to loose track of work being done around another significant front end language—SystemC.  For those not aware, …

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