Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.

 IP Showcase  by Peggy Aycinena
Peggy Aycinena
The Tate Effect: Confidence in Flex Logix Team & Technology
  Geoff Tate, founding CEO at Rambus, is busy – again. These days he’s leading the charge with a new FPGA-based enterprise that, per Tate, wants to be “the first to the party” – a party that’s all about providing FGPA-based IP …

 What Would Joe Do?  by Peggy Aycinena
Peggy Aycinena
PCB Tools, Part 2: Request for info
Last year a blog was posted in this space talking about tools for PCB design: PCB Tools, Part 1: Zuken, Mentor, Cadence, Altium. Lengthy and detailed, that discussion included commentary on the state of the art, and the market, for PCB design …

 Custom Layout Insights  by Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells, Director of Product Marketing at Synopsys
Custom Compiler In-Design Assistants (Part 3)
In the blog 'Custom Compiler In-Design Assistants (Part 2)', I outlined how we can use StarRC to report capacitances on critical nets in the layout even when the design is still in flux and not completely LVS-clean. In addition to capacitance …

 Embedded Software  by Colin Walls
Colin Walls
Device registers in C
Mentor Graphics has historically been dedicated to providing tools for electronic hardware designers and that still represents a very large proportion of the business. Ever since I was acquired into the company, I have found that the hardware …

 Hardware Emulation Journal  by Lauro Rizzatti
Lauro Rizzatti
Great Ideas, Solid Information Exchange Define DVCon India
In its third year, DVCon India 2016 was held in Bangalore September 15-16, hosted in the Leela Palace, as it was in 2015, an island of serenity, peace and comfort in the center of Bangalore. Although I don’t want to repeat myself, my 2015 …

 Aldec Design and Verification  by Radek Nawrot, Software Product Manager
Radek Nawrot, Software Product Manager
Aldec Engineers: Taking Action and Giving Back as a Team
For engineers, the importance of keeping active cannot be understated. When thousands of hours are spent seated in front of monitors, healthy activities such as running are more than fun... they are necessary. At Aldec, our team enjoys combining …

 The Breker Trekker  by Adnan Hamid, CEO of Breker
Adnan Hamid, CEO of Breker
User Victory in Portable Stimulus
As regular readers know, the Portable Stimulus Working Group (PSWG) of the Accellera System Initiative has been working for some time to develop a new way to define verification intent once and to be able to reuse that across all stages of the …

 Bridging the Frontier  by Bob Smith, Executive Director
Bob Smith, Executive Director
What Keeps You Awake at Night?
While many things keep me awake at night, concerns about IP tracking and security must keep many chip project managers from getting a restful sleep. That’s what convinced Warren Savage, chair of the ESD Alliance’s Semiconductor IP Working Group …

 EDA Careers Corner and News  by Mark Gilbert
Mark Gilbert
WOW, DAC Was Better Than I Thought…BIZ Has Picked Up Since DAC….The Amazing “Peggy” Wrote About Yours Truly…
Let me start by thanking Peggy Aycinena for her article. It was nice to have the tables turned on me by one of our brightest; take a look… …

 Real Talk  by Lisa Piper, Senior Technical Marketing Manager at Real Intent
Lisa Piper, Senior Technical Marketing Manager at Real Intent
Fix X-pessimism in Netlists with Practical Techniques
Most functional verification is done before the RTL is handed off for digital synthesis. Gate-level simulations take longer and are hard to debug, but still needed to verify some circuit behavior. Ideally, the output of the RTL simulation will match …

 Decoding Formal  by Pippa Slayton
Pippa Slayton
Another Reason to Stay an Extra Day in Austin
If you are attending the Design Automation Conference (DAC) in Austin, Texas, June 5-9, and need a good reason to stay an extra day, look no further. Oski Technology is offering a one-day primer on advanced formal verification techniques at the …

 Guest Blogger  by Chuck Alpert - the General Chair for the 53rd DAC
Chuck Alpert - the General Chair for the 53rd DAC
#53DAC, 7: Fly brains, trillion-transistor devices and tales from a Steve Jobs alum
All of a sudden it’s nearly the end of April, high time to switch from months to weeks (just six to go now!) in the countdown to DAC, which I can guarantee is going to be a great conference. One big reason I’m confident is that, as always, we …

 What's PR got to do with it?  by Ed Lee
Ed Lee
What is in-situ de-embedding?
As a follow up to Chris Scholz’s predictions on 2016 signal integrity trends, we checked in with in-situ de-embedding inventor Dr. Ching-Chao Huang, who gives us a more detailed look at how engineers will need to handle signal integrity …

 Analog Insights  by Hélène Thibiéroz
Hélène Thibiéroz
Q&A with Altera: How to improve your advanced-node design productivity using Synopsys SPICE Simulation and Analysis environment
Greetings, You may have noticed from my previous post that we had a very successful event in Austin. I therefore wanted to share with you some of the technical content.  One of the aspects we cover is the increasing amount of analysis and …

 The Dominion of Design  by Sanjay Gangal
Sanjay Gangal
Median Income of Electrotechnology, IT Professionals Rises to $130,000 for Largest Gain in Past Five Years
Article source: IEEE Median income for electrotechnology and information technology professionals jumped by more than 4 percent in 2014, the largest increase in the past five years, according to the 2015 IEEE-USASalary & Benefits …

 Video Roundup  by Susan Smith
Susan Smith
HP Announces HP Z240 Tower and Z240 SFF Workstations
Jeff Wood - vice president, WW Product Management,  Workstation and Thin Client Business HP and Josh Peterson- director, WW Product Management,  Workstation and Thin Client Business , HP met with the press in a virtual press briefing prior to the …

 Verification Futures  by Mike Bartley
Mike Bartley
DVCon India expected to welcome over 600 delegates
The second DVCon India Conference is expecting to welcome over 600 delegates , up from 450 last year for the first conference. It is running in Bangalore on September 10th and 11th. But why should you be there too? 39 technical papers and 15 …

 Core Values  by Neil Parris
Neil Parris
7 things I learned at 52DAC
Last week I attended the Design Automation Conference as an intrepid reporter to put my ear to the ground and take note of what is happening in the industry. I wrote some daily review blogs of my time on the show floor (which can be seen here, Day …

 Disrupted Hard  by Matthieu Wipliez
Matthieu Wipliez
Numbers don’t lie: there is virtually no interest in high level synthesis
I finally read enough articles about high level synthesis (HLS) that give a sense of hype that just didn't seem to be matched by what I've heard. Now hype is pretty subjective, but numbers are not. For example, the High Level Synthesis group on …

 ExcelliBlog  by Rick Eram, Sales & Marketing VP
Rick Eram, Sales & Marketing VP
Value of timing constraints files beyond STA
Timing Constraint files are one of the best timing and clock data containers available to the designers, yet they are under utilized today and their value is not fully exploited in the design flow. The timing information captured in timing …

 The Instigater: Services with a Smile  by Arman Poghosyan
Arman Poghosyan
EDA Application Porting Guide: Part 1
Introduction With this article we would like to start a series of tutorials covering the migration of EDA applications from Windows to Mac OS X and GNU/Linux. For that purpose we will review the technologies for building user-interface, data layer …

 ASIC with Ankit  by Ankit Gopani
Ankit Gopani
Class – The Classic Feature – Part II
Dear AWA Readers Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test …

 NOT EDA  by Sanjay Gangal
Sanjay Gangal
Satya Nadella Named Microsoft CEO
Article source: Microsoft Corp. & Wikipedia Microsoft Corp. today announced that its Board of Directors has appointed Satya Nadella as Chief Executive Officer and member of the Board of Directors effective immediately. Nadella previously …

 It's Verific !  by Michiel Ligthart
Michiel Ligthart
The demise of VHDL has been greatly exaggerated
I don’t recall when it was the first time that I heard VHDL was a dying language, but for sure it was many years ago, maybe as far back as the late 1990s. Obviously the EDA futurists of then got it very wrong, and I was recently wondering if I …

 AWR Insights  by Sherry Hess
Sherry Hess
AWR: Redefining Design
When I first learned of NI’s Redefining campaign, I thought… yes, makes perfect sense and fits AWR extremely well. Our company was founded almost 20 years ago on the very idea of redefining design for microwave/RF engineers. We began this …

 Dispatches from Boston  by Nanette Collins
Nanette Collins
OneSpin Reaches for the Cloud
As the 50th Design Automation Conference opens, attendees rushing through the doors early Monday may have their heads in a Cloud. Cloud computing that is, and heading straight toward Booth #846. That’s because OneSpin Solutions in Booth #846 …

 Verification is No Simulation  by Dave Rich
Dave Rich
Get your IEEE 1800-2012 SystemVerilog LRM at no charge
At this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge …

 Industry Commentary  by Dr. Russ Henke
Dr. Russ Henke
The EDA and MCAD/MCAE Almanac – Nominal Q3 2012 Part B: MCAD/MCAE Industry
Dear faithful blog reader: Please take a few minutes of your valuable time to read the January 31, 2013 article, “The EDA and MCAD/MCAE Almanac - Nominal Q3 2012 Part B: MCAD/MCAE Industry” You may reach the new January 31 Commentary by …

 IEEE CEDA Corner  by Joel Phillips
Joel Phillips
Alberto Sangiovanni-Vincentelli Celebrates ICCAD’s 30th Anniversary with Look Back at EDA
CEDA turned to Alberto Sangiovanni-Vincentelli of the University of California, Berkeley, to help us celebrate the 30 anniversary of the International Conference in Computer-Aided Design (ICCAD). And, he didn’t disappoint. In a rousing talk …

 EDA Thoughts  by Daniel Payne
Daniel Payne
DAC 2011 Trip Reports – Mostly Transistor Level Tools
2011 was the year of the foundry (TSMC, Globalfoundries, Samsung) at DAC in San Diego. The foundries had bigger booths, bigger events, were on more panel sessions, and had more marketing influence than any other year that I can remember. The …

 Global Business in EDA  by Mo Casas
Mo Casas
Are you missing the opportunity to go global? These tips will signal if you are ready
Expanding business overseas is important. If you are a small EDA vendor, going global before you are ready can be suicidal. Here are some signals that can help you decide you if you are ready to go global. Have you been successful at …

 Become Your Customers  by Saranyan Vigraham

 Open Electrons  by Chitlesh Goorah (Free Electronic Lab)
Chitlesh Goorah (Free Electronic Lab)
Milkymist: pushing further the limits of electronics openness
Everyone has heard of open source software, but can the same principles be applied to hardware? Some people argue that hardware is so expensive to manufacture and modify that it prevents hobbyists from contributing, and thus stifles …

 Stan on Standards  by Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski, Group Director of Standards, Cadence
Japan & SystemC
With all of the excitement in the “front end” of the SOC design/verification/modeling community about Accellera’s UVM, it is easy to loose track of work being done around another significant front end language—SystemC.  For those not aware, …


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
PCB Tools, Part 2: Request for info
More Editorial  
Electronics Firmware / Digital DesignEngineer 2 for Northrop Grumman at Rolling Meadows,, IL
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Upcoming Events
2016 GreenBuild International Conference and Expo at Los Angeles Convention Center Los Angeles CA - Oct 5 - 6, 2016
DASIP 2016 at Rennes France - Oct 12 - 14, 2016
SystemC AMS & COSIDE® User Group Meeting 2016 at Maritim Hotel Munich Germany - Oct 18, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy