Part Number : dwc_mipi_dphy_slave_2l-tsmc_40lp18
Short Desc. : MIPI DPHY Slave 2 Data Lanes - TSMC 40LP 1.8V
Overview :
The DesignWare & reg; MIPI D-PHY is a fully integrated core implemented either with fully bidirectional lanes or as a Receive only configuration, optimized for CSI-2 Host or DSI Device implementations. Designed to conform to the latest MIPI D-PHY specification, it includes all the analog and digital circuitry delivered as a fully verified hard macro. The standard configuration includes 1 Clock Lane and 2 data lanes supporting each a maximum 1Gbps in high-speed mode. It supports multiple low power mode including shut down and provides multiple test modes for increased reliability. The IP implements the MIPI recommended Protocol Peripheral Interface (PPI) to ensure ease of integration with the protocol controller layer. The DesignWare MIPI D-PHY provides a high-reliability high-speed differential interface reducing line count and minimizing cable wires and EMI shielding requirements and is an ideal solution for MIPI CSI-2, DSI and UniPro interfaces.
Features : - Compliant with MIPI D-Phy Interface Specification, rev. 1.0
- Fully integrated hardmacro
- Up to 1Gbps per lane
- Up to 4 Data lanes
- Protocol Peripheral Interface (PPI)
- Low power Escape modes and ultra Low Power Modes
- Shutdown mode
- SCAN and Loopback BIST modes
- Extensive access to internal programmability registers
Categories :
Maturity : Silicon proven
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - Databook
- Application notes
- Assembly guidelines
- Design files kit: Behavioral model; .LEF file; .LIB file; GDSII layout database
S2C: FPGA Base prototyping- Download white paper

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