Part Number : dwc_adciq12b80m_tsmc28hpmns
Short Desc. : [34891ts-hpm] 12-bit, 80MSPS, 0.9V High Speed SAR IQ-ADC in TSMC 28HPM
Overview :
With more than 15 years of experience in developing analog IP solutions, Synopsys offers a comprehensive portfolio of more than 100 silicon-proven DesignWare ® Data Converter IP products consisting of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), auxiliary converters, video DACs (VDACs) and analog front-ends (AFEs). Synopsys' strong application expertise in areas such as mobile communications and wireless connectivity (i.e., LTE/LTE-A, WiFi.11n, WiFi.ac), wireline communications (i.e., G.hn, MoCA), IF demodulation, multimedia, imaging and video, and sensors and embedded applications, enables us to deliver high-quality data converter IP that helps system-on-chip (SoC) designers meet the specific design requirements for their target applications. The DesignWare Data Converter IP products offer very high performance, high speed, ultra low power dissipation, small area use, and support for a wide range of foundry process technologies ranging from 180-nm to 28-nm. Synopsys' high-quality DesignWare Data Converter IP solutions have been implemented in more than 200 SoCs, giving designers confidence that they can successfully integrate high-performance analog IP into their designs with less risk and improved time-to-market
Features : - High Resolution, High Speed
- Wideband Input Interface
- Compact, Low Power
- Standard Digital CMOS with no Analog Options
- #1 provider of data conversion IP for six years in a row (Gartner, 2010)
- Over 13 years of expertise in designing differentiated data conversion solutions
- Strong application expertise in broadband wireless communications, wired communications, video, etc
- Proven ADC/DAC technology
- Extensive offering: Oversampling Sigma-Delta ADC, Pipeline ADC, SAR ADC, Current Steering DAC, and more
- Very high-performance, high-speed 12-bit @ 250 MSPS ADC and 14-bit @ 400 MSPS DAC, small area and delivering ultra low power dissipation
Categories :
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - Verilog Behavioral Model
- LEF Layout Abstract and LIB Timing Models
- GDSII Layout Database
- CDL netlist for LVS verification
- Detailed Databook, Assembly Guidelines and Full Integration Support

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