HDL Design House 
Overview :

The MIPI Tx M-PHY is a high frequency, low power IP compliant with the MIPI Alliance Standard forM-PHY version 1.0. It can be used as Physical Layer for interfaces such as camera, display, audio,video, power management and communication between BB (Base Band) and RFIC. It's used totransmit data and clock on to the differential Tx lane. The high frequency clock is generated by theTx PLL. The MIPI Tx M-PHY support two modes of data transmission: HS (High Speed) and PWM LS(Pulse Width Modulation Low Speed).

Features : - IInput clock frequency for MPHY Type I : 19.2MHz, 26MHz, 38.4MHz, 52MHz
- Input clock frequency for MPHY Type II : 19.2MHz, 26MHz, 38.4MHz for DigRF 3G
- Input clock frequency for MPHY Type II : 26MHz, 38.4MHz, 52MHz for DigRF V4
- MIPI M-PHY Type I is available in 28nm and 40nm
- MIPI M-PHY Type II is available in 40nm and 65nm
- Support all HS modes (Gear 1 - 3)
- Support PWM mode up to Gear 6 for 40nm technology
- Support PWM mode up to Gear 7 for 28nm technology
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy