Digital Blocks, Inc. 
Part Number : DB9000AHB
Short Desc. : AHB Bus TFT LCD Controller
Overview :

The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD panel. In an FPGA, ASIC, or ASSP device, the microprocessor is an ARM processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM. Figure 1 depicts the system view of the DB9000AHB TFT LCD Controller IP Core embedded within an integrated circuit device. 

Features : - Wide range of programmable LCD Panel resolutions
- Support for 1 Port TFT LCD Panel interfaces
- Programmable frame buffer bits-per-pixel (bpp) color depths
- Color Palette RAM to reduce Frame Buffer memory storage requirements and AHB Bus bandwidth
- Programmable Output format support
- Programmable horizontal timing parameters
- Programmable vertical timing parameters
- Programmable pixel clock
- Programmable Data Enable timing signal
- Power up and down sequencing support
- 9 sources of internal interrupts with masking control
- Little-endian, big-endian, or Windows CE mode
- Compliance with AMBA Specification (Rev 2.0)
- Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, No gated clocks, and No internal tri-states
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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