The core is a complete module intended for use in FPGA system vision projects. It works as follows. The core is connected to the interface controller of DDR memory via a standard interface (controller provided by Xilinx Company) from which it reads the current images of video sequence and where it writes the results. The designer should ensure refreshment of image frames in the DDR memory according to multi-buffer principle (multiple buffering). Before
operation is started, the core should be configured (configuration register values need to be written). Capture of objects for tracking and rejection from tracking is carried out by a command.
The core supports independent tracking of up to 5 objects. Sizes of the tracking strobes are set
separately for each object and can be changed in the course of tracking.