Silicon Library Inc. 
Overview :
SLI ZRSLSIPSDUHS2PHY is PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface for both SDHC and SDXC.

By using SLI's unique SerDes technology, ZRSLSIPSDUHS2PHY achieves 300MB/s that is the maximum speed for UHS-II with the low power consumption.
Features : - Bi-directional receiver/transmitter (2ch) supporting both Full Duplex and Half Duplex modes
- 390Mbps to 1.56Gbps/ch
- (Upper Range: 780Mbps ~ 1.56Gbps, Lower Range: 390Mbps ~ 780Mbps)
- RCLK frequency: 26~56MHz
- Power Supply Voltage: 1.0V/3.3V
- Operating Temperature (Tj): -40degreeC ~ 125degreeC
- Clock Recovery
- 8B10B
- On-chip termination resistors
- Link parallel interface selectable between 8b or 16b
- Programmable PHY parameters
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy