Test And Verification Solutions 
Short Desc. : TVS UART UVM VIP
Overview :
Test and Verification Solutions offers a UART UVM VIP as part
of its asureVIP™ series of offerings. This is a highly flexible and
configurable verification IP, which can be easily integrated into
any SOC verification environment. The TVS UVM Master VIP
(AXI4-LITE) supports UART and UART16550 Modes. It was
used in successfully verfying a DUT, later silicon proven.
Features : - Independently controlled transmit,
- receive, line status, and data set
- interrupts.
- Programmable baud generator divides
- any input clock by 1 to (2^16 - 1) and
- generates the 16 clock.
- Independent receiver clock input.
- MODEM control functions (CTS, RTS,
- DSR, DTR, RI and DCD).
- Fully programmable serial-interface
- characteristics:
- 5-, 6-, 7-, or 8-bit characters
- Even, odd, or no-parity bit generation
- and detection
- 1-, 1(/2-, or 2-stop bit generation
- Baud generation (DC to 1.5M baud).
- False start bit detection.
- Complete status reporting capabilities.
- TRI-STATEÉ TTL drive for the data
- and control buses.
- Line breaks generation and detection.
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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