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 Test And Verification Solutions 
Short Desc. : TVS I2C OVM/UVM MASTER VIP
Overview :
Test and Verification Solutions offers an I2C OVM/UVM Master
VIP as part of its asureVIP™ series of offerings. This is a highly
flexible and configurable verification IP, which can be easily
integrated into any SOC verification environment. The I2C
OVM/UVM Master VIP supports standard, fast and high speed
modes of operation. It also supports 7-bit and 10-bit addressing
modes. The Master VIP has been interoperability tested with a
Slave VIP configuration. This slave VIP was used in
successfully verifying a DUT, later silicon proven.
Features : - Each slave device connected to the bus is
- software addressable by a unique address
- and simple master/slave relationships exist
- at all times.
- It’s a true multi-master including collision
- detection and arbitration to prevent data
- corruption if two or more masters
- simultaneously initiate data transfer.
- Serial, 8-bit oriented, bi-directional data
- transfers can be made at up to 100 Kbit/s
- in the Standard-mode, up to 400 Kbit/s in
- the Fast-mode, or up to 3.4 Mbit/s in the
- High-speed mode.
- Addressing Modes Supported (7-bit, 10-bit
- & general call address).
- Clock Synchronization of more than two
- masters connected to the I2C Bus.
- Repeated Start Generation Scenarios
- Bus monitor has capability to detect Illegal
- Start/Stop/Repeated Start Conditions.
- Bus monitor has capability to detect Illegal
- Start/Stop/Repeated Start Conditions.
Categories :
Portability :
Type : Soft
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