Login

 IPClock 
Short Desc. : IEEE1588 BC and OC
Overview :
The IPC9000 utilizes IPClock’s state-of-the-art technology for IEEE1588v2 optimized for providing high quality frequency synchronization and Time of Day (ToD) over packet switched networks.
Features : - * Standalone IEEE1588v2 standard compliant Boundary Clock and Master/Slave Ordinary Clock chip on FPGA
- * Hybrid 1588/SyncE mode support
- * ToD alignment error is better than ±1µsec on a managed 10-switch
- * Standard compliant Best Master Clock (BMC) algorithm
- * Easy implementation of master redundancy
- * Master flexible reference clock input frequencies: 1PPS, 1.544MHz, 2.048MHz, or 10MHz
- * Master can lock to undisciplined 1PPS signal from GPS
- * Slave four programmable clock outputs: 1.544MHz, 2.048MH, or 10MHz
- * Upgradeable by software
- * Excellent performance with low cost oscillator
- * Easily integrates in existing and next generation designs
- * Provides precision holdover
- * Easy adding of enhancements and supporting emerging clock synchronization standards
Categories :
Portability :
Type : Soft
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy