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 Arrow Devices 
Short Desc. : JEDEC UFS Device Verification IP
Overview :

Arrow Devices’ JEDEC UFS 2.0 Device Verification IP de-risks your JEDEC UFS-2.0 Device development effort by providing a high degree of confidence over all the design features before shipping silicon. JEDEC UFS-2.0 is a verification challenge as it has to support several UFS SCSI commands, task management commands and interaction with the underlying service delivery mechanism that consists of MIPI UniPro 1.6 and MIPI M-PHY 3.0. Our JEDEC UFS-2.0 Device Verification IPs provides the relevant BFMs and a full feature test-bench with ready-made compliance and random test-suits, coverage and assertion suits.

 
Arrow Devices' USB 2.0 Verification IP is currently being used by some of top global semiconductor companies and has helped these companies ship bug-free silicon.

Features : - Specification: JEDEC UFS 2.0, UME 1.0
- UVM test-bench with pre-written compliance and constrained random test suite
- BFM implementation: Native SystemVerilog
- BFM methodology Support: UVM, OVM, VMM
- Simulator support: Synopsys VCS, Mentor Graphics Questa
- Configurability: Supports both the UFS Host and Device Verification
- Supports testing with JEDEC UTP + MIPI UniPro 1.6 + MIPI M-PHY 3.0
- Supports all SAPs: UIO, UDM, UTP_CMD, UTM_TM, UBM
- Supports all UPIU types and UTP Protocol Checks − Supports all JEDEC UFS SCSI commands, task management and device management requests
- Supports UTRD and UTMRD
- Supports all UMPIU types and UME Protocol Checks
- Supports LUNs and W-LUNs (including boot functionality)
- Provides programmable descriptors
- Provides built in scheduling
- Provides built-in error injection
- Provides events for synchronization
- Provides callbacks for arbitration and command scheduling customization
- Provides callbacks for the coverage/scoreboard
Categories :
Tags : JEDEC UFS
Maturity : Multiple customers
Portability :
Type : Soft
Deliverables : - All Relevant BFMs
- Comprehensive Test bench
- Comprehensive Test Suite (Directed and Constrained Random)
- Comprehensive Coverage Suite
- Protocol Level Debugging Tool (Protocol Debug Assistant)
- Documentation
- User Guide
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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