True Circuits 
Part Number : TCI-CL90LP-DSLPLL
Short Desc. : GF/CP L90LP 90nm Deskew PLL - 75MHz-375MHz
Features : - Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
Categories :
Maturity : Silicon proven
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
S2C: FPGA Base prototyping- Download white paper

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