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Short Desc. :
SD 3.0 / eMMC 4.51 Host Controller
The Posedge SD 3.0/eMMC 4.51 host controller core is a highly configurable Host Controller compatible with Standard SD Host Specification Version 3.0, SD Physical Layer Specification Version 3.0 and eMMC Specification Version 4.51. The Host Controller supports Sd and eMMC Interfaces The PE-SDMMCH controller supports 1-bit , 4 bit modes and 8bit mode for SD/MMC embedded applications. The Controller is designed to operate in at maximum operating frequency of 208MHz (SD) / eMMC(200MHz) to achieve maximum throughput of 104 MBytes/sec for SD and 200MBytes/sec for eMMC devices.
The Controller supports Programmed IO mode (PIO), Simple DMA (SDMA)and powerful scatter / gather DMA (ADMA) for data transfer. The Controller supports AHB Interface and works in DMA Mode of operation to transmit and receive data. The AHB Slave Interface is used for register programming and PIO operation. Using the PE-SDMMCH Core, the Host driver can access memory up to 2TBytes.
The PE-SDMMCH has two bus interfaces, the System Bus Interface and the SD Bus interface. The PE-SDMMCH assumes that these interfaces are asynchronous. The Host Controller synchronizes signals to communicate between these interfaces.
The PE-SDMMCH Core is designed for low power, high performance, less gate count making it ideal for low-power and high-performance applications.
The PE-SDMMCH core was tested using rigorous verification methodology, consisting of directed tests, constrained random verification, and Error Injection cases.
- Compliant with
- Standard SD Host Specification 3.0
- SD Physical Layer Specification 3.0
- eMMC Specification 4.51
- AMBA Specification 2.0
- Supports SD Bus Width 1-bit, 4-bit , SPI Mode and Optional 8bit mode for SDIO embedded applications
- Supports SD Single Data Rate and Dual Data Rate modes (SDR12, SDR25, SDR50, SDR104, DDR50)
- Supports SD Memory Access up to 2TB (SDXC)
- Supports CMD20 for Speed Class Recording
- Supports Clock Tuning
- Supports eMMC Boot Operation and Alternate Boot Operation mode
- Entire Core can run on Low Power Clock during power saving mode
- SD Clock Gating
- Supports SDSC / SDHC / SDHS / SDXC Cards
- Supports Up to 7 Slots
- Supports SD features Erase, Password Protection and Write protection feature
- Supports Asynchronous Interrupt for data transfers
- Supports PIO / SDMA and ADMA Operation
- Cyclic Redundancy Check (CRC) for command and data
- Configurable 32-bit FIFO buffers (512B – 2KB)
- Data Transfer Rate – Up to 832Mbps
- SD Clock – Up to 208 MHz and AHB Clock – Up to 300MHz (process dependent)
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