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Digital Blocks, Inc.
Part Number :
The Digital Blocks DB-I2C-S-RA Controller IP Core implements an I2C Slave
Controller, with a user parameterized Register Array for embedded user I/O Control & Status within an ASIC / ASSP / FPGA device. The DB-I2C-S-RA Controller implements the Slave-Transmit and Slave-Receive protocol according to the I2C-Bus Specification, Version 2.1.
- *I2C Slave Controller - Implements Slave-only protocol for smaller VLSI footprint, for applications requiring Slave–Receiver and Slave–Transmitter capability
- *Parameterized Register Array which interfaces to the DB-I2C-S-RA Controller for receiving and transmitting data. DB-I2C-S-RA Controller supports single register access or burst access with address auto-increment capability.
- *7- or 10-bit addressing
- *Digital filter for the received SDA and SCL lines
- *Supports three I2C bus speeds:
--Standard mode (100 Kb/s)
--Fast mode (400 Kb/s)
--Fast mode plus (1 Mbit/s)
- *Compliance with I2C specifications:
--Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000
- *Fully-synchronous, synthesizable Verilog-2001 or VHDL RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.
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