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Digital Blocks, Inc.
Part Number :
The Digital Blocks DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS,
PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 AXI
System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
- *I2C Master only with Parameterized FIFO:
- *Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:
- *For Transmits, the processor writes the Slave Address & bytes of information into the FIFO, sets a start control bit, and waits for an interrupt or polls a status bit signaling completion
- *For Receive, the processor writes the Slave Address into the DB-I2C-M-AXI, sets a start control bit, and waits for an interrupt or polls a status bit signaling completion. The processor then reads the bytes of information from the FIFO.
- *Small VLSI footprint. Master Controller Modes:
- *Master – Transmitter
- *Master – Receiver Parameterized 8-bit FIFO for higher performance. Optional 16 or 32-bit processor interface. Supports two I2C bus speeds:
- *Standard mode (100 Kb/s)
- *Fast mode (400 Kb/s)
- *Fast mode plus (1 Mbit/s)
- *7 sources of internal interrupts with masking control
- *Compliance with AMBA 2.0 and I2C specifications:
- *AMBA AXI Protocol Specification (V2.0)
- *Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000
- *Fully-synchronous, synthesizable Verilog or VHDL RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.
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