Digital Blocks, Inc. 
Part Number : DB-I2C-MS-AHB
Overview :
The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AMBA AHB Bus to an I2C Bus. The I2C is a two-wire bidirectional interface
standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
Features : - Master / Slave I2C Controller Modes:
- Master – Transmitter
- Master – Receiver
- Slave – Transmitter
- Slave – Receiver Parameterized FIFO memory for off-loading the I2C transfers from the processor:
- Targets embedded processors with high performance algorithm requirements, by the I2C Controller independently controlling the Transmit or Receive of bytes of information buffered to and from a FIFO. Supports three I2C bus speeds:
- Standard mode (100 Kb/s)
- Fast mode (400 Kb/s)
- Fast mode plus (1 Mbit/s) 7 sources of internal interrupts with masking control Compliance with AMBA and I2C specifications:
- Compliance with AMBA Specification 2.0 – AHB
- Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000
Categories :
Portability :
Type : Soft
CST: Webinars Begin on February 9
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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