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 Truechip Solutions Pvt. Ltd. 
Short Desc. : I2C Verification IP
Overview :

Truechip's I2C Verification IP provides an effective & efficient way to verify the components interfacing with I2C interface of an ASIC/FPGA or SoC.


Features : - Full compliant with Revision 3.0 and 2.1 of the I2C-Bus Specification
- Full I2C Master and Slave functionality
- Master Transmitter/Master Receiver
- Slave Transmitter/Slave Receiver
- START, repeat START and STOP for all possible transfers
- Supports all Speed Modes: Standard Speed Mode (upto 100 kb/s), Fast Speed Mode (upto 400 kb/s), Fast Speed Mode Plus (upto 1Mb/s) and High Speed Mode (upto 3.4 Mb/s)
- Supports 7-Bit and 10-Bit addressing format
- Allows testing of varied bus traffic for Read,Write, General Call
- Supports scoreboard feature for end to end data integrity check
- Notifies the Testbench of significant events such as transactions, warnings, and protocol errors Ø Built in I2C BusMonitor provides extensive protocol checking
- Support Multi-Master and Multi-Slave system
- Supports Arbitration and Clock Synchronization
- Support START Byte, Device ID, Bus Clear and Clock Stretching
- Supports various error injection and detection
- Provides verification scalability using functional coverage
- Provides logging facility for bus traffic in the ASCII format and in user configurable mode
- Supports Callback in Master, Slave and Monitor
- Supports timing checks in the Monitor
Categories :
Tags : I2C Verification IP, I2C VIP, I2C
Maturity : Available
Portability :
Type : Soft
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