Short Desc. : ULP OTP Memory
Overview :
Sidense OTP memory IP is based on a patented, area-efficient antifuse 1T-FuseTM cell employing gate oxide breakdown as a programming mechanism. Available in a standard CMOS process, Sidense macrocells do not require any additional mask layers or process steps.
Features : - • Standard CMOS Logic Process 1.8V core, 3.3V IO voltage
- • Up to 2Kbits per macrocell
- • Multiple macrocells can be combined for larger OTP sizes
- • Up to 128 IO bits per macrocell
- • Optional Integrated Power Supply (IPS)
- • Ultra low read power consumption
- • Power-On Read function
- • Built-in word-line test mode
- • Built-in bit-line test mode
- • Built-in sense amplifier test mode
- • Built-in cell margin modes for programming verification
Categories :
Portability :
Type : Soft
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