Short Desc. : ULP OTP Memory
Overview :
Sidense OTP memory IP is based on a patented, area-efficient antifuse 1T-FuseTM cell employing gate oxide breakdown as a programming mechanism. Available in a standard CMOS process, Sidense macrocells do not require any additional mask layers or process steps.
Features : - • Standard CMOS Logic Process 1.8V core, 3.3V IO voltage
- • Up to 2Kbits per macrocell
- • Multiple macrocells can be combined for larger OTP sizes
- • Up to 128 IO bits per macrocell
- • Optional Integrated Power Supply (IPS)
- • Ultra low read power consumption
- • Power-On Read function
- • Built-in word-line test mode
- • Built-in bit-line test mode
- • Built-in sense amplifier test mode
- • Built-in cell margin modes for programming verification
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy