Noesis Technologies 
Part Number : ntTPC
Overview :
In channel coding redundancy is inserted in the transmitted informa-tion bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPE) and the Turbo Product Decoder (ntTPD) blocks.
Features : - Programmable data block size by adjusting codeword dimen-sions, i.e. number of rows and number of columns.
- Supports shortening by adjusting number of rows and columns to be eliminated in order to create a shortened code.
- Programmable number of soft bits in the input data.
- 2’s complement arithmetic data format.
- Supports extended Hamming or single parity constitu-ent codes.
- Supports (64,57), (32,26), (16,11) or (8,4) extended Hamming constituent codes.
- Supports (64,63), (32,31), (16,15) or (8,7) single par-ity constituent codes.
- Programmable number of algorithmic iterations.
- Supports user selectable synchronous reset.
- Fixed encoder and decoder latency.
- Supports ASIC and FPGA implementation technologies.
- Single edge, fully synchronous design.
- Area efficient design.
- Silicon proven in Xilinx FPGA technologies for a variety of applications.
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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