SmartDV Technologies 
Short Desc. : PCIE VIP
Overview :
PCIE Verification IP provides an smart way to verify the PCIE bi-directional bus. The SmartDV's PCIE Verification IP is fully compliant with version 1.0/2.0/3.0 of the PCIE Specification and provides the following features.
Features : - Supports PCIE Express specs 1.0/2.0/3.0.
- Supports PIPE, Serial, PCS/PMA, and serdes interface.
- Supports Full link speed and width negotiation up to 32 Lanes.
- Supports Automated Error Injections at all layers.
- Supports Checkers verify protocol timing checks and functional accuracy at each layer.
- Supports Queuing for 8 VCs with configurable depth.
- Supports Configurable TC to VC queue mapping.
- Supports for multiple Requestor / Completer applications, including user supplied applications.
- Supports User interface for direct TLP queuing and receipt.
- Supports Checks all TLPs for correct formation of headers, prefixes, and ECRC.
- Supports Full DL state machines.
- Supports Checks all framing, LCRC, and lane rules.
- Supports Check all DLLP fields and formatting.
- Supports Interface to send / receive user defined DLLPs.
- Supports ASPM and Software controlled Power Management.
- Supports Automated Error Injections and checking.
- Supports Full LTSSM state machine.
- Supports SERDES model with digital clock recovery.
- Supports Speed and Link Width negotiation.
- Supports Upconfigure, polarity inversion, and lane-to-lane skew.
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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