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Short Desc. :
PE-SMIH -- SD3.01/SDIO 3.0/eMMC 4.51 Host Controller
The Posedge SDXC/SDIO/eMMC (PE-SMIH) is a highly configurable Host Controller compatible with Standard SD Host Specification Version 3.0, SDIO Specification Version 3.0, SD Physical Layer Specification Version 3.01 and eMMC Specification Version 4.51. The Host Controller supports three key Interfaces namely SD, SDIO and eMMC. The PE-SMIH controller supports SD/MMC 1, 4, bit modes and 8bit mode for SDIO / MMC embedded applications. The Controller is designed to operate in at maximum operating frequency of 208MHz (SD) / eMMC(200MHz) to achieve maximum throughput of 104 MBytes/sec for SD and 200MBytes/sec for eMMC devices.
The Controller supports Programmed IO mode (PIO), Simple DMA (SDMA)and powerful scatter / gather DMA (ADMA) for data transfer. The Controller supports AHB Interface and works in DMA Mode of operation to transmit and receive data. The AHB Slave Interface is used for register programming and PIO operation. Using the PE-SMIH Core, the Host driver can access memory up to 2TBytes.
The PE-SMIH has two bus interfaces, the System Bus Interface and the SD Bus interface. The PE-SMIH assumes that these interfaces are asynchronous. The Host Controller synchronizes signals to communicate between these interfaces.
The PE-SMIH Core is designed for low power, high performance, less gate count making it ideal for low-power and high-performance applications.
The PE-SMIH core was tested using rigorous verification methodology, consisting of directed tests, constrained random verification, and Error Injection cases.
- Supports PIO, SDMA, and ADMA modes of operation.
- Customizable clock frequency and transfer rates.
- SD 3.0
- All UHSI modes - SDR50/SDR104/DDR50
- Clock Tuning
- All slot types (Removable / Embedded Slot / Shared Bus Slot)
- Asynchronous interrupt support and programmable clock generator
- SDSC/SDHC/SDXC/SDHS cards
- Regular boot operation mode
- Alternate boot operation mode
- Access to boot/RPMB/general purpose partition
- MMC plus and MMC mobile cards
- General Features
- Read Wait
- Tap delay circuit
- Backward compatible
- Number of slots [1 / 2]
- Buffer size [DPRAM/SPRAM, 512B/1KB/2KB]
- System interface [AHB/APB]
- Data transfer [PIO/DMA/ADMA/Slave DMA]
- SD/MMC bus width [1,4, 8] bits
- Low Power features
- Entire IP can run on sleep clock, during power saving mode (KHz range)
- Wake up events for card insertion, card removal, and card interrupt SD clock gating
- Clock frequency and transfer rates
- 208MHz – SD/SDIO/MMC clock
- KHz range sleep clock
- Up to 832Mbits/sec
- Highly Configurable IP
- Highly Customizable
- Low Gate Count
- World Class Support
- Fully synthesizable RTL
- Self-checking Test-bench and Testcases
- Verification specification
- ASIC/FPGA synthesis scripts
- User Documentation
- Integration Manual
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