Mercora Technologies 
Short Desc. : SHA-512 Fast IP Core (Xilinx)
Overview :
The SHA-512 Fast IP Core provides a hardware implementation of the Secure Hash Algorithm (SHA-512). The SHA-512 algorithm belongs to a group of five secure iterative hash algorithms recommended by NIST as part of their Secure Hash Standard (FIPS 180-3). The SHA-512 hash can accept messages up to 2^128-1 bits in length and returns a 512-bit message digest.

The SHA-512 Fast IP Core provides a balance between high throughput and size. The Fast IP core comes with a 64/512-bit IO interface and integrated padding logic. The core is designed for applications that need high throughput, low latency, and reduced power consumption.
Features : - Implements SHA-512 secure hash algorithm specified by NIST FIPS 180-3
- Synchronous 64/512-bit IO interface (byte oriented)
- Integrated padding logic
- High throughput requires only 82 clock cycles per 1024-bit hash block
- Small hardware footprint for reduced power consumption
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy