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Short Desc. :
IEEE 802.11n/802.11ac (WiFi) LDPC Decoder
The IEEE 802.11n/ac standards require high data rates of up to 600 Mbit/s for 802.11n and up to 7 Gbit/s for 802.11ac. The Creonic LDPC decoder achieves data rates of hundreds of Mbit/s even on low-cost FPGAs. Therefore it ideally suited to satisfy the high demands on forward error correction of the 802.11n and 802.11ac standards.
Altogether, the decoder supports twelve different LDPC codes: Three different block lengths (648 bits, 1296 bits, and 1944 bits) each with four different code rates (1/2, 2/3, 3/4, 5/6). Because of the iterative LDPC decoding algorithm, the 802.11n/ac decoder achieves a gain of up to 3 dB in comparison to Viterbi decoders. The IP core is suitable for FPGA as well as ASIC technologies.
- Compliant with IEEE 802.11n-2009.
- Compliant with IEEE P802.11ac (draft).
- Support for all LDPC code rates (1/2, 2/3, 3/4, 5/6).
- Support for all LDPC block lengths (648, 1296, and 1944 bits).
- Gains up to 3 dB compared to Viterbi decoders.
- Low-power and low-complexity design.
- Layered LDPC decoder architecture, for faster convergence behavior.
- Block-to-block on-the-fly configuration.
- Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy.
- Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance.
- Collection of statistic information (number of modified information bits, number of iterations, decoding successful).
- Available for ASIC and FPGAs (Xilinx, Altera).
- Deliverable includes VHDL source code or synthesized netlist, VHDL or SystemC testbench, and Matlab, C or C++ bit-accurate simulation model.
Forward Error Correction
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