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Short Desc. : HDMI v1.4 Transmitter IP Core
Overview :
The primary function of the HDMI transmitter is to implement the HDMI formatting of the input video and audio data, and interface to a serializer for direct transmission onto the HDMI cable. This IP core supports HDCP authentication and synchronization, identification of the RX capabilities via E-EDID on the DDC, hot plug detection, and a simplified implementation of the CEC protocol.
The IP is composed of an HDMI 1.4 core and its physical Layer devices (PHY) in 65nm, 40nmLP, and 28nmLP technologies.
Features : - DP SST and MST compliant
- Includes frame formatter, HDCP, CEC and hot plug detection
- SD/ED/HD, 3D video and VESA formats up to 297 MHz pixel clock
- Support for deep color - 8, 10, 12, 16 bits per video component
- Pixel repetition: one, two, three and four
- Video input - 4:4:4 YCbCr or RGB up to 16-bit per component, 4:2:2 YCbCr 12-bit per component
- Audio interface : four S/PDIF or I2S ports, audio sampling rates up to 192 KHz
- Up to 8-channel IEC60958 PCM audio, IEC61937 LBR compressed audio - up to 192-KHz (DD+) and high bit rate audio up to 768 KHz (DTS-HD, Dolby TrueHD)
- Hot plug detection generates an interrupt/wakeup state whenever the HPD input
- pin toggles
- Full adherence to the HDCP authentication and encryption, including fast authentication
- TMDS/BCH encoding performed in hardware
- Flexible ACR packet transmission - CTS value provided by hardware or software
- DFV observability using MISR calculation on
- the 10-bit digital outputs to the serializer
- Exhaustive serializer test logic - software bypass, PRPG, JTAG/Tap controller direct interface
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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