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Short Desc. : HDMI v1.4 Receiver IP Core
Overview :
The HDMI Receiver IP provides the integrated functionality to interface with an HDMI compliant source and extract the corresponding video and audio signals. The HDMI RX IP design provides a solution for receiving data from a link in accordance with DVI and HDMI 1.1/1.2/1.3/1.4 with 3D interfaces using HDCP 1.3 encryption. The IP is composed of the HDMI v1.4 core and physical
layer device (PHY), in 65nm, 40nmLP and 28nmLP technologies.
Features : - • Receives all possible audio formats from the HDMI1.4 standard and extracts the sample rate clock
- • Supports link rates from 25 MHz to 165 MHz (DVI/HDMI1.1), up to 225MHz for HDMI1.3/1.3a and up to 297 MHz for HDMI1.4
- • Supports all 3D video formats
- • Color Spaces: RGB, YUV444, YUV422, xvYCC
- • Automatic video/audio type detection and mute generation
- • Color depth: all defined in HDMI 1.4 (up to 48 bpp in the RGB color space)
- • Up/Down color depth dithering at the video output
- • Automatic video screen blocking using a programmed background color during video mute
- • Internal image format measurement block
- • Packet receiving and storing for MCU access of all standard types with possibility of automatic error correction and filtration
- • Automatic HDCP link decryption of video data based on provided keys
- • Automatic HDCP noise detection schemes for HDMI modes
- • Automatic processing of packets such as GCP, ACR
- • Automatic clock correction circuits allow clock regeneration and adjustment task
- • Source plug-in detection based on HPD voltage level
- • DDC2BI support on selected ports
- • Embedded pattern generator for test
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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