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Short Desc. : DSI Host IP core (HIP 3500)
Overview :
DSI (Display Serial Interface) defines protocol between host processor and a peripheral such as Display device, based on MIPI Alliance specifications for mobile devices interfaces, which operates with pixels and command sets specified in the DPI-2, DBI-2 and DCS standards. Its purpose is to send pixels and commands to the peripheral such as Display and receives back pixel or status information from the peripheral.
Features : - • Transfers pixels and data received from DBI or DPI or AHB interface to the peripheral such as display via DSI D-PHY.
- • Supports MIPI DSI protocol version 1.02
- • Supports MIPI DCS version 1.02
- • Supports MIPI DBI version 2.0
- • Supports MIPI DPI version 2.0
- • Supports MIPI D-PHY version 1.0
- • Max. data rate 800 Mbps per data lane
- • Supports up to 4 data lanes (minimum is one data lane) and one clock lane
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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