Overview :
The Secure Clock Generator IP is an analog IP that provides a secure, adjustable and autonomous clock. The clock is generated independently and does not require external crystal. The Secure Clock Generator IP includes a frequency monitor and a clock glitch detector in order to detect any attempt to tamper with the circuit's clock.
Features : - Adjustable at selected frequencies in the 200 MHz to 600 MHz range
- Very low footprint : 0,1 mm2 (65nm process)
- Accuracy +/- 5% - (+/- 1% can be achieved at greater footprint)
- Jittered clock protects against side channel attacks
- Clock glitch detector protects against fault-injection attacks
- Clock monitor outputs alarm outside of specified clock range
- Power consumption : 2mA typical at 600 MHz (65nm process)and 1 µA standby (65nm process)
Categories :
Portability :
Type : Hard
Deliverables : - GDSII
S2C: FPGA Base prototyping- Download white paper

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