||- Compliant with IEEE 802.15.3c-2009 standard.
- Suitable for single carrier (SC) mode and high speed interface (HSI) mode.
- Support for all short LDPC codes (672 bits, code rates 1/2, 5/8, 3/4, 7/8).
- Block-to-block on-the-fly configuration.
- Low-power, high-throughput, and low-latency design.
- Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy.
- Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance.
- Collection of statistic information (number of iterations, decoding successful).
- Available for ASIC and FPGAs (Xilinx, Altera).
- Deliverable includes VHDL source code or synthesized netlist, VHDL or SystemC testbench, and Matlab, C or C++ bit-accurate simulation model.