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 Digital Core Design 
Part Number : DQ80251
Overview :

DQ80251 is a revolutionary Quad-Pipelined ultra high performance, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The core has been designed with a special concern for performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU. This product is build based on 13 years of DCD’s know-how with triumphant 8051 architectures. DQ80251 soft core is 100% binary-compatible with the industry standard 16-bit 80C251 and 8-bit 80C51 microcontrollers. There are two working modes of the DQ80251: BINARY where original 80C51 compiled code is executed, and SOURCE which is native 80C251 mode using all DQ80251 performance. DQ80251 has build-in configurable DoCD-JTAG on chip debugger supporting Keil DK251 and standalone DoCD debug software. Dhrystone 2.1 benchmark program runs 66 times faster than the original 80C51 and more than 5 times faster than the original 80C251 at the same frequency. This performance can be also exploited to great advantage in low power applications where the core can be clocked over fifty times slower than the original implementation for no performance penalty. Additionally compiled code size for SOURCE mode is about 2 times smaller comparing to identical standard 8051 code, since DQ80251 instructions are more effective.


Features : 100% binary compatible with industry standard 80C251 implementing BINARY and SOURCE modes Single clock period per most of instructions Quad-Pipelined architecture enables to execute 65.67 times faster than the original 80C51 and 5.34 times faster than 80C251 at the same frequency Up to 61.8 VAX MIPS at 100 MHz Up to 8M bytes of Program Memory Up to 32k bytes of internal (on-chip) Data Memory Up to 8M bytes of external (off-chip) Data Memory Up to 16 MB of total memory space for CODE and DATA 64k bytes of extended stack space User programmable Program Memory Wait States solution for wide range of memories speed User programmable Extended Data Memory Wait States solution for wide range of memories speed De-multiplexed Address/Data bus to allow easy connection to memory Full Program Memory writes Interface for additional Special Function Registers DoCD debug unit:
  • Processor execution control
  • Read-write all processor contents
  • Hardware execution breakpoints
  • JTAG communication interface
Power Management Unit:
  • Power management mode
  • Switchback feature
  • Stop mode
Interrupt Controller:
  • 4 priority levels
  • 2 external interrupt sources
  • 3 interrupt sources from peripherals
Four 8-bit I/O Ports:
  • Bit addressable data direction for each line
  • Read/write of single line and 8-bit group
Two 16-bit timer/counters:
  • Timers clocked by internal source
  • Auto reload 8-bit timers
  • Externally gated event counters
Full-duplex serial port:
  • Synchronous mode, fixed baud rate
  • 8-bit asynchronous mode, fixed baud rate
  • 9-bit asynchronous mode, fixed baud rate
  • 9-bit asynchronous mode, variable baud rate
Fully synthesizable Static synchronous design Positive edge clocking and no internal tri-states Scan test ready
Categories :
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria GX
Arria II GX
Cyclone
Cyclone III
FLEX 10K
HardCopy
HardCopy II
HardCopy Stratix
MAX II
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
Stratix IV
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - Source code: VHDL Source Code or/and VERILOG Source Code or/and FPGA Netlist
- VHDL & VERILOG test bench environment: Active HDL automatic simulation macros, ModelSim automatic simulation macros, NCSim automatic simulation macros, Tests with reference responses
- Technical documentation: Installation notes, HDL core specification, Datasheet
- Synthesis scripts
- Example application
- Technical support: IP Core implementation support, 3 months maintenance, Delivery the IP Core updates, minor and major versions changes, Delivery the documentation updates, Phone & email support
CST Webinar Series



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