Aizyc Technology 
Short Desc. : AIZYC SD_SDIO_eMMC host controller IP
Overview :
Highly configurable SD/SDIO/eMMC host controller IP with AHB/OCP/VCI/eMMC 4.41 interface
Features : - Conforms to SD Physical Layer Specifications version 3.01
- support to eMMC4.41 interface
- System Interface – AHB
- Optional Interface – VCI,OCP,AXI, APB
- Supports SDR25, SDR50, SDR104 and DDR50 modes of operation
- Supports up to 104MBps speed
- In-built clock divider
- Assumes external PLL for implementations that choose to use multiplier for greater accuracy of clock frequency
- Configurable FIFO depth
- Supports shared SD bus to connect up to 3 devices
- Supports 1.8V, 3.3V and 3.0V operation. Chip pads are 1.8V. Board level solution is required to support 3.3V and it is controlled by a GPIO pin
- Supports Interrupt
- Supports stop at block gap
- Supports 32-bit AHB slave interface for register configuration and data transfer
- AHB slave interface supports INCR and FIXED address bursts
- Supports DMA channel Req/Ack to integrate with external DMA
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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