|MVD takes advantage of the advanced FPGA features and development techniques for very high performance DSP functions implementation.
The Spartan-6, Virtex-5 and Virtex-6 architectures provide advanced features necessary for this very high speed (4GHz+) advanced Up Converter.
Among those important features :
• Powerful and flexible slice logic
• Very fast distributed memory & block RAM
• Embedded cascadable DSP bocks
• High speed clocks managements
• IO SERDES & LVDS IOs for 1GHz+ data rate while working at lower speed in the FPGA fabric
Required resources depend on the number of channel groups and channels per group to be modulated.
As an example, the input streams can be base band I & Q signals sampled at 131.25 MHz.
Each channel is then modulated at a low Intermediate Frequency as follows : for 6MHz wide channels grouped by 4, the respective IF frequencies can be –9MHz, -3MHz, +3MHz and +9MHz. This group behaves as a 24MHz wide base band channel (Intermediate Frequency = 0MHz).
To reach 1050 Mbits/sec on the 4 x 12 links from the FPGA to the MAX5881 RF DAC (working @4.2 Gsps), the Spartan-6, Virtex-5 or Virtex-6 IO SERDES allow to distribute the several output phases of the modulator with precharacterized performance (independently of Place & Route optimization) : In those families, all IOs have an embedded ISERDES and OSERDES, able to work in SDR or DDR mode. They support 1050 Mbits/s rate, while serializing internal data (4 to 1 or 8 to 1 in our case), originally sampled at much lower frequency (131.25 MHz for Spartan-6 or 262.5 MHz for Virtex-5 and Virtex-6).