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 HDL Design House 
Short Desc. : CML RapidIO SerDes IP core (HIPA 21000)
Overview :
The use of Rapid IO supporting IP cores speeds the design cycle, increases design quality and allows greater degree of innovation, enabling companies to reduce design costs and create market differentiation. Although this IP is designed to be used with SRIO 2.1 HIP3100 IP core (developed by HDL Design House), it can be used by any digital interface which satisfies timing parameters.
Features : - Single 1.8V power supply voltage
- Extracted clock from received data is available
- Rapid IO standard 2.1 is supported. Data rate from 1.25Gbaud/s to 6.25 Gbaud/s are possible
- Operating temperature satisfies industrial temperature range (-40°C to 85°C)
- Adaptable data transfer rate
- Parallel data 20 bit wide
- Modular design
- Minimal external components
- Programmable Tx
Categories :
Portability :
Type : Soft
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