||- 8 state 3GPPTM LTE compatible turbo encoder
- Rate 1/3
- 40 to 6144 bit interleaver
- Up to 222 Mbit/s encoding speed
- Parallel encoded data out
- 218, 218 and 129 slices for Spartan–3A, Virtex–4 and Virtex–5, respectively. Other Xilinx devices also supported.
- Available as EDIF core and VHDL simulation core for Xilinx FPGAs under SignOnce IP
- License. Actel, Altera and Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
- Low cost university license also available