||- Supports standard, fast, and high speed operations.
- Full I2C Master and Slave functionality.
- Supports packet error checking for SMBus mode
- Supports ARP sequence for SMBus mode
- Operates as a Master, Slave, or both.
- Monitor, Detects and notifies the testbench of all protocol and timing errors.
- Supports all I2C clocking speeds
- 7b/10b configurable slave address
- Compares read data with expected results
- Bus-accurate timing
- Various kind of Master and Slave errors generation
- Glitch monitor and injection.
- Supports timeouts forcing and handling in SMBus mode
- Callbacks in master and slave for various events.
- Status counters for various events in bus.