SmartDV Technologies 
Short Desc. : RapidIO VIP
Overview :
RapidIO Verification IP provides an smart way to verify the RapidIO bi-directional two-wire bus. The SmartDV's RapidIO Verification IP is compliant with RapidIO Trade Association, RapidIO Interconnect Specification version 1.3 and 2.0. RapidIO VIP is implemented in a layered fashion. Whichis basically divided into a physical layer, transport layer and logical layer. The SmartDV's RapidIO Verification IP has both the incarnations of RapidIO technology :Parallel RapidIO and Serial RapidIO(SRIO).
Features : - Supports RapidIO specification 1.3,2.0 and 2.1.
- Supports Serial 1x/2x/4x/8x and 16x Physical lanes.
- Supports XTBI like interface for testing after PCS layer.
- Supports XGMII like interface for testing before PCS layer.
- Supports 3.125 Gbaud/s, 2.5 Gbaud/s, 1.25 Gbaud/s.
- 66, 50, or 34-bit addressing on the RapidIO interface.
- Supports Parallel Physical 8/16 bits interfaces.
- Supports all types of packets and sizes.
- Supports 8-bit or 16-bit device IDs
- Automatic freeing of resources used by acknowledged packets
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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