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 Xilinx 
Short Desc. : Virtex-6 Integrated Block for PCI Express (PCIe)
Overview :
Xilinx provides a Virtex-6 FPGA Endpoint solutions for PCI Express® (PCIe) to configure the Virtex-6 FPGA Integrated Block for PCIe FPGA and includes additional logic to create a complete solution for PCIe. This Xilinx Block Wrapper for PCIe simplifies the design process and reduces time-to-market. Many easy-to-use features and optimal configuration for Endpoint and Root Port applications are available at no additional cost.
Features : - Compliant with the PCI Express Base Specification 2.0
- Fully compliant with PCI Express transaction ordering rules
- Supports maximum payload of 1024 bytes (for most configurations)
- 1 Virtual Channel
- Supported Lane width: x1, x2, x4 and x8
- Bandwidth scalability interconnect width
- Pre-implemented optimal buffering for high bandwidth applications
- LocalLink User Interface for easy bridging to other Xilinx IP
- Uses Virtex-6 GTX Transceivers
- Design verified by a Xilinx proprietary testbench
Categories :
Portability :
Type : Soft
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